ASIC Design/Verification Engineer Hewlett-Packard - Bangalore


Job Description

The roles & responsibilities includes verification ofcomplex RTL models at a module level / System level using SystemC /SystemVerilog / SpecMan E as theverification Language for the SoCs for the compute domain environment.
This requires stimulus generation in a randomizedenvironment to exercise the relevant features and help in releasing a highquality chip for fabrication. It also involves development of test verificationcomponents like generators, checkers and topologies inC++/SystemVerilog/SystemC.
Engineers at this job will also be involved in Post SiliconValidation of the chipsets in a lab environment as well.
Domain Knowledge
Verification of multi-million gate ASICs/SoC, HardwareDesign Validation at module level and system levels
Knowledge of Computer System Architecture; Working experience in developing theverification environment

Desired Skills & Experience

Ability to develop verification plans, create block, fullchip and system level test suites, run regressions
Working knowledgeof any source code control system on Linux
Gate level simulations, Netlist Validation, Hardwareverification & debugging

Tools/Languages
SystemC /SystemVerilog, C++, Verilog, SpecmanE
Protocols like PCIX/PCIEX/IPSec, Cache Coherence
Scripting with Perl/Shell , Python
Cadence, Synopsys toolset
Apply Now - Resume or CV with Job Post Title
Email: jobs@aarenconsultants.in
Location: Bengaluru, Karnataka, India

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